Field of the Invention
The present invention relates generally to structures and methods of manufacturing dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) MOS (metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C.
Dislocations are defects in crystal structures, and disadvantageously can provide current paths for leakage currents in bulk silicon and SOI CMOS devices having such dislocations.